VLSI Design: 2008

Friday, May 23, 2008

Analog BJT And CMOS Circuit Design

Theory of Differential Amplifier:

VLSITechnology.org offers free Standard cell library in 350nm and 130nm Release V 8.5 Compatable with Alliance Cad Systems

Site Content

This site contains support material for a book that Graham Petley is writing, The Art of Standard Cell Library Design.

This material includes standard cell libraries, which are made available under the terms of the GNU Lesser General Public Licence. There are no restrictions on using these libraries in an integrated circuit, and they can be copied, modified and distributed under terms of your choice provided that the original copyright is prominently displayed (see section 6 of the licence).

Standard cell library information

There are five new open source standard cell libraries, the vsclib, wsclib, vxlib, vgalib and rgalib. They have been drawn with the Graal software from Alliance, part of an extensive open source software suite for designing integrated circuits with a standard cell design methodology.

The libraries have been characterised in a generic 0.13µm technology. The spice model comes from the University of California, Berkeley.

The layout has been drawn using MOSIS layer numbers and names and the pharosc rule set, and then scaled to what are slightly oversized 0.13µm rules which should be compatible with most foundries.

The vxlib is compatible with the sxlib created by the Alliance software authors. The vsclib is a completely new library design. The wsclib is derived from the vsclib. The rgalib and vgalib are small gate array type libraries.

The Alliance sxlib has also been characterised in 0.13µm using the same methodology and converted to the same 0.13µm layout rules. There is also an ssxlib which is the Alliance sxlib converted with a script from 1µm to 2µm layout and adjusted to obey DSM layout rules. The adjustments change the timing slightly.

The characterisation methodology creates a web data book, and this is on-line with the cells' layout and schematics.

Recent releases

In Release 8.1, the wsclib and ssxlib have been added. There are variants called stxlib, vtxlib, vtclib and wtclib which allow routing on the metal-1 level. See the examples directory in the release file for more details.

Release 8.2 has increased the size of the vsclib and wsclib, improving a number of the cell layouts and adding a D flip‑flop. Two small gate array libraries have also been added.

Release 8.3 has added a latch to the vsclib and wsclib, and expanded the examples directory. Each cell's fixed delay in the Alliance VBE file used for VHDL simulation has been set to the cell delay driving 25fF.

Release 8.4 has some small corrections and help files for working from a Linux Live CD.

Release 8.5 has much improved support for Magic including a single tech file, updated DRC files, completely revised extraction parameters and extraction flow which avoids the previous kludge, and improved colours for viewing the cells.

For more references visit www.vlsitechnology.org

Thursday, May 22, 2008

Perl The Ultimate laguage for anything including VLSI Design

Perl is a programming language created by Larry Wall and first released in 1987. Perl inherited features from a variety of other languages including C, shell scripting (sh shell), AWK, sed and Lisp.

VLSI DESIGN With PERL

Now lets talk about the ultimate ease in VLSI Design. The regular expression feature of Perl is so easy to implement an understandable that a very good parser can be written by a fresher programmer. And parsers can be made usable VLSI Designs as Verilog2VHDL converter or some format conversions can be made very easily.

I have created a fully automated tool for VLSI Layout & Tiling creation of different kind of GDS2 Design in perl . It can be used for Standard Cell creation, Memory Compiler Creation, & Custom Designing. Very soon I will be publishing it to internet for free for Researchers, Students and Professors.

A Moderately Strong but Free VLSI Tool Set for ASIC & MEMORY Designs From ASIM LIP6 Group

Alliance is a complete set of free CAD tools and portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools. A complete set of portable CMOS libraries is provided. Alliance is the result of a twelve year effort spent at ASIM department of LIP6 laboratory of the Pierre et Marie Curie University (Paris VI, France). Alliance has been used for research projects such as the 875 000 transistors StaCS superscalar microprocessor and 400 000 transistors IEEE Gigabit HSL Router.

Alliance VLSI CAD System is free software. Binaries, source code and cells libraries are freely available under the GNU General Public License (GPL). You are welcome to use the software package even for commercial designs without any fee. You are kindly requested to mention : "Designed with Alliance © LIP6, Université Pierre et Marie Curie"

For downloading and more reference go to http://www-asim.lip6.fr/recherche/alliance/

Logical Effort, the way to Digital Circuit Design

The method of logical effort, a term coined by Ivan Sutherland and Robert Sproull in 1991, is a straightforward technique used to estimate delay in a CMOS circuit. Used properly, it can aid in selection of gates for a given function ( sizing gates to achieve the minimum delay possible for a circuit.

Derivation of delay in a logic gate

Delay is expressed in terms of a basic delay unit, τ = 3RC, the delay of an inverter driving an identical inverter with no parasitic capacitance; the unitless number associated with this is known as the normalised delay. The absolute delay is then simply defined as the product of the normalised delay of the gate, d, and τ:

d a b s = d τ

In a typical 600-nm process τ is about 50 ps. For a 250-nm process, τ is about 20 ps.

The normalised delay in a logic gate can be expressed as a summation of two primary factors: parasitic delay, p (which is an intrinsic delay of the gate and can be found by considering the gate driving no load), and stage effort, f (which is dependent on the load as described below). Consequently,

d = f + p

The stage effort is divided into two components: a logical effort, g, which is the ratio of the input capacitance of a given gate to that of an inverter capable of delivering the same output current (and hence is a constant for a particular class of gate and can be described as capturing the intrinsic properties of the gate), and an electrical effort, h, which is the ratio of the input capacitance of the load to that of the gate. The stage effort is then simply:

f = g h

Combining these equations yields a basic equation that models the normalised delay through a single logic gate:

d = g h + p

Multistage logic networks

A major advantage of the method of logical effort is that it can quickly be extended to circuits composed of multiple stages. The total normalised path delay D can be expressed in terms of an overall path effort, F, and the path parasitic delay P (which is the sum of the individual parasitic delays):

D = F + P

The path effort is expressed in terms of the path logical effort G (the product of the individual logical efforts of the gates), and the path electrical effort H (the ratio of the load of the path to its input capacitance).

For paths where each gate drives only one additional gate (i.e. the next gate in the path),

F = G H

However, for circuits that branch, an additional branching effort, b, needs to be taken in to account; it is the ratio of total capacitance being driven by the gate to the capacitance on the path of interest:

$b = \frac{C_{onpath} + C_{offpath}}{C_{onpath}}$

This yields a path branching effort B which is the product of the individual stage branching efforts; the total path effort is then

F = B G H

It can be seen that b = 1 for gates driving only one additional gate, fixing B = 1 and causing the formula to reduce to the earlier non-branching version.

Minimum delay

It can be shown that in multistage logic networks, the minimum possible delay along a particular path can be achieved by designing the circuit such that the stage logical efforts are equal. For a given combination of gates and a known load, B, G, and H are all fixed causing F to be fixed; hence the individual gates should be sized such that the individual stage efforts are

f = F 1 / N

where N is the number of stages in the circuit.

Examples

Delay in an inverter

A CMOS inverter circuit.

By definition, the logical effort g of an inverter is 1. If the inverter drives an equivalent inverter, the electrical effort h is also 1.

The parasitic delay p of an inverter is also 1 (this can be found by considering the Elmore delay model of the inverter).

Therefore the total normalised delay of an inverter driving an equivalent inverter is

d = g h + p = (1)(1) + 1 = 2

Delay in NAND and NOR gates

The logical effort of a two-input NAND gate is calculated to be g = 4/3 because a NAND gate with input capacitance 4 can can drive the same current as the inverter can, with input capacitance 3. Similarly, the logical effort of a two-input NOR gate can be found to be g = 5/3. Due to the lower logical effort, NAND gates are typically preferred to NOR gates.

For larger gates, the logical effort is as follows:

Logical effort for inputs of static CMOS gates, with gamma = 2
Gate type	1	2	3	4	5	n
	Number of Inputs
Inverter	1	N/A	N/A	N/A	N/A	N/A
NAND	N/A	$\frac{4}{3}$	$\frac{5}{3}$	$\frac{6}{3}$	$\frac{7}{3}$	$\frac{n + 2}{3}$
NOR	N/A	$\frac{5}{3}$	$\frac{7}{3}$	$\frac{9}{3}$	$\frac{11}{3}$	$\frac{2n + 1}{3}$