VLSITechnology.org offers free Standard cell library in 350nm and 130nm Release V 8.5 Compatable with Alliance Cad Systems

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This site contains support material for a book that Graham Petley is writing, The Art of Standard Cell Library Design. This material includes standard cell libraries, which are made available under the terms of the GNU Lesser General Public Licence. There are no restrictions on using these libraries in an integrated circuit, and they can be copied, modified and distributed under terms of your choice provided that the original copyright is prominently displayed (see section 6 of the licence). Standard cell library information There are five new open source standard cell libraries, the vsclib, wsclib, vxlib, vgalib and rgalib. They have been drawn with the Graal software from Alliance, part of an extensive open source software suite for designing integrated circuits with a standard cell design methodology. The libraries have been characterised in a generic 0.13µm technology. The spice model comes from the University of California, Berkeley. The layout has been drawn using MOSIS layer numbers and names and the pharosc rule set, and then scaled to what are slightly oversized 0.13µm rules which should be compatible with most foundries. The vxlib is compatible with the sxlib created by the Alliance software authors. The vsclib is a completely new library design. The wsclib is derived from the vsclib. The rgalib and vgalib are small gate array type libraries. The Alliance sxlib has also been characterised in 0.13µm using the same methodology and converted to the same 0.13µm layout rules. There is also an ssxlib which is the Alliance sxlib converted with a script from 1µm to 2µm layout and adjusted to obey DSM layout rules. The adjustments change the timing slightly. The characterisation methodology creates a web data book, and this is on-line with the cells' layout and schematics. Recent releases In Release 8.1, the wsclib and ssxlib have been added. There are variants called stxlib, vtxlib, vtclib and wtclib which allow routing on the metal-1 level. See the examples directory in the release file for more details. Release 8.2 has increased the size of the vsclib and wsclib, improving a number of the cell layouts and adding a D flip‑flop. Two small gate array libraries have also been added. Release 8.3 has added a latch to the vsclib and wsclib, and expanded the examples directory. Each cell's fixed delay in the Alliance VBE file used for VHDL simulation has been set to the cell delay driving 25fF. Release 8.4 has some small corrections and help files for working from a Linux Live CD. Release 8.5 has much improved support for Magic including a single tech file, updated DRC files, completely revised extraction parameters and extraction flow which avoids the previous kludge, and improved colours for viewing the cells. For more references visit www.vlsitechnology.org