VLSI DESIGN With PERL
Now lets talk about the ultimate ease in VLSI Design. The regular expression feature of Perl is so easy to implement an understandable that a very good parser can be written by a fresher programmer. And parsers can be made usable VLSI Designs as Verilog2VHDL converter or some format conversions can be made very easily.
I have created a fully automated tool for VLSI Layout & Tiling creation of different kind of GDS2 Design in perl . It can be used for Standard Cell creation, Memory Compiler Creation, & Custom Designing. Very soon I will be publishing it to internet for free for Researchers, Students and Professors.
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